AMD UMI and PCIe Bridge Register Access Method

If we want to access the UMI and the FCH/GPP link interface could through the following register spaces: ABCFG, AXCFG, AXINDC, AXINDP, RCINDC, and RCINDP

Change the register spaces must through the AB_INDX/AB_DATA register pair. You can get the AB_INDX through PM_REG that IO index port 0xCD6 and IO data port 0xCD7 offset 0xE0 register.

For example, if the PM_REG offset 0xE0 is 0xCD8 that means the AB_INDX is 0xCD8 and AB_DATA is equal to AB_INDX + 4.

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AXINDC Registers:

AX_INDXC 0x30

AX_DATAC 0x34

Example 1: For Write Temp to AXINDC 20h

Out CD8h, 00000030h

Out CDCh, 00000020h

Out CD8h, 00000034h

Out CDCh, Temp

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AXINDP Registers:

AX_INDXP 0x38

AX_DATAP 0x3C

Example 2: For Write Temp to AXINDP 20h

Out CD8h, 40000030h

Out CDCh, 00000020h

Out CD8h, 40000034h

Out CDCh, Temp

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AXCFG Registers:

Example 3: For Write Temp to AXCFG 03h

Out CD8h, 80000003h

Out CDCh, Temp

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ABCFG Registers:

Example 4: For Write 0xFFFFFFFF to ABCFG 04h

Out CD8h, C0000004h

Out  CDCh, FFFFFFFFh

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RCINDC Registers:

Example 5: For Write Temp to RCINDC 14h

Out CD8h, 20000014h

Out CDCh, Temp

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RCINDP Registers:

Example 6: For Write Temp to RCINDP A0h(PortB)

Out CD8h, 610000A0h

Out  CDCh, Temp