;Input:
; eax - function code 0E820H
; ebx - continuation code, zero for first call
; es:di - buffer pointer , point to an buffer for BIOS to fill in.
; ecx - buffer size , minimum is 20 bytes
; edx - signature 'SMAP'
C:\debug32
-r32
-a
mov eax, 0000e820
mov ebx, 0
mov ecx, 14
mov edx, 534d4150
mov di, 200
int 15
int 3
p
-go
;Output:
; CF - non-carry indicates no error
; eax - signature return 'SMAP'
; es:di - buffer pointer, same as input
; ecx - real buffer size return
; ebx - continuation code , zero return if last run occured
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Monday, May 30, 2011
Thursday, May 26, 2011
ACPI can't recogize OS type with Ubuntu operating system
ACPI can't recogize OS type with Ubuntu operating system
Remove "Linux" from supported _OSI strings.
The Linux OS no longer wants to respond true for this string.
The only safe strings are windows-related as they represent the tested path through the BIOS-provided ASL.
===========================================================================
現在Ubuntu不支援用_OSI strings的方式來回報OS類型
Remove "Linux" from supported _OSI strings.
The Linux OS no longer wants to respond true for this string.
The only safe strings are windows-related as they represent the tested path through the BIOS-provided ASL.
===========================================================================
現在Ubuntu不支援用_OSI strings的方式來回報OS類型
Monday, May 23, 2011
A20 Gate
1. 在8086的系統,當初只設計20根位址線。透過Segment + Offset的方式來定址,Ex. F000 : 0010h = F0000+ 0010h = F0010h 那衍生了一個問題就是當CS : IP的值為FFFF : FFFFh = FFFF0 + FFFFh = 10FFEFh = 1M + 64K – 16 Bytes 但系統只能存取到1M以下,這該如何是好? 所以大於1M,系統會直接回繞。
2. 在80286的系統,位址線變成了24根,但又要向下相容,就衍生了A20的模式,當A20是disable,就等同於8086的架構,若A20 Enable,系統就可以存取到2 ^ 24次方 = 16M byte,也就是Segment變成最大值為FFFFFh 而不是FFFFh
3. 開啟A20 Gate的方法,最簡單就是對IO Port 92h 的bit 1給設起來;反之關閉A20 Gate的方法,就是清掉IO Port 92h 的bit 1。
enable_A20:
cli
call a20wait
mov al,0xAD ; Disable Keyboard
out 0x64,al
call a20wait
mov al,0xD0
out 0x64,al
call a20wait2
in al,0x60
push eax
call a20wait
mov al,0xD1
out 0x64,al
call a20wait
pop eax
or al,2
out 0x60,al
call a20wait
mov al,0xAE ; Enable Keyboard
out 0x64,al
call a20wait
sti
ret
a20wait:
in al,0x64
test al,2
jnz a20wait
ret
a20wait2:
in al,0x64
test al,1
jz a20wait2
ret
3. 開啟A20 Gate的方法,最簡單就是對IO Port 92h 的bit 1給設起來;反之關閉A20 Gate的方法,就是清掉IO Port 92h 的bit 1。
enable_A20:
cli
call a20wait
mov al,0xAD ; Disable Keyboard
out 0x64,al
call a20wait
mov al,0xD0
out 0x64,al
call a20wait2
in al,0x60
push eax
call a20wait
mov al,0xD1
out 0x64,al
call a20wait
pop eax
or al,2
out 0x60,al
call a20wait
mov al,0xAE ; Enable Keyboard
out 0x64,al
call a20wait
sti
ret
a20wait:
in al,0x64
test al,2
jnz a20wait
ret
a20wait2:
in al,0x64
test al,1
jz a20wait2
ret
Wednesday, May 18, 2011
RTC Lost Power
After remove RTC coin battery, system plug-in RTC coin battery the CMOS register 0xE access by (index port 0x70/ data port 0x71) bit 7 will be set. After check this bit, we also need to clear this bit by code.
============================================================================
在移除RTC水銀電池後,然後再次插上,這時後CMOS register offset 0xE的位址,在(使用index port 0x70/ data port 0x71)方式存取,這時候的0xE的bit 7會被設起來,在code裡面,一檢查完,就需要清掉這個位元。
============================================================================
在移除RTC水銀電池後,然後再次插上,這時後CMOS register offset 0xE的位址,在(使用index port 0x70/ data port 0x71)方式存取,這時候的0xE的bit 7會被設起來,在code裡面,一檢查完,就需要清掉這個位元。
Tuesday, May 17, 2011
About IO Decode (AMD Chipset)
1.Set IO base address in south bridge register
2.Enable Alternative Wide IO Range in south bridge register
3.Enable Wide IO Port in south bridge register
if system still can't open IO decode, we need to check is occupied by another device using the same IO resource or not. We can check the value in each of PCI bridge offset 0x1C.PCI bridger IO resource is aligned to a 4KB boundary.
============================================================================
1.設定要做IO decode去設定南橋暫存器的IO Base Adress
2.開啟南橋暫存器的Alternative Wide IO Range
3.開啟南橋暫存器的Wide IO Port
若還是無法開啟IO decode,這時候就要檢查是否有別的device佔用到相同的IO decode的位址,可以先檢查每個PCI bridge的offset 0x1C的值,PCI bridge一次就是佔4K的IO resource。
2.Enable Alternative Wide IO Range in south bridge register
3.Enable Wide IO Port in south bridge register
if system still can't open IO decode, we need to check is occupied by another device using the same IO resource or not. We can check the value in each of PCI bridge offset 0x1C.PCI bridger IO resource is aligned to a 4KB boundary.
============================================================================
1.設定要做IO decode去設定南橋暫存器的IO Base Adress
2.開啟南橋暫存器的Alternative Wide IO Range
3.開啟南橋暫存器的Wide IO Port
若還是無法開啟IO decode,這時候就要檢查是否有別的device佔用到相同的IO decode的位址,可以先檢查每個PCI bridge的offset 0x1C的值,PCI bridge一次就是佔4K的IO resource。
Monday, May 16, 2011
The Different Between LegacyBiosInt86 And LegacyBiosFarCall86
When we wanna issue a software interrupt, we need to call LegacyBiosInt86 thunk function call.
When we wanna jump to OPROM or other legacy address, we need to call LegacyBiosFarCall86 thunk function call.
========================================================================
LegacyBiosInt86是我們需要使用程式去呼叫INT時所使用到的thunk function ,像是CALL INT10...
LegacyBiosFarCall86是我們需要跳到option ROM address所需要用到的thunk function
When we wanna jump to OPROM or other legacy address, we need to call LegacyBiosFarCall86 thunk function call.
========================================================================
LegacyBiosInt86是我們需要使用程式去呼叫INT時所使用到的thunk function ,像是CALL INT10...
LegacyBiosFarCall86是我們需要跳到option ROM address所需要用到的thunk function
Tuesday, May 10, 2011
Bring Up BIOS
1. Modify GPIO that depends on platform design
2. Modify FDLA (Firmware Device Linear Address)
3. Change VBIOS
4. Change SPI ROM size
5. Disable KSC
===========================================================================
做一個Bring-up BIOS主要的工作如下:
1. 依照platform的layout去修改GPIO
2. 修改FDLA (Firmware Device Linear Address)
3. 換掉VBIOS
4. 依照platform的設計改變SPI ROM大小
5. 移除KSC
2. Modify FDLA (Firmware Device Linear Address)
3. Change VBIOS
4. Change SPI ROM size
5. Disable KSC
===========================================================================
做一個Bring-up BIOS主要的工作如下:
1. 依照platform的layout去修改GPIO
2. 修改FDLA (Firmware Device Linear Address)
3. 換掉VBIOS
4. 依照platform的設計改變SPI ROM大小
5. 移除KSC
Friday, May 6, 2011
ACPI Enable and Disable Behavior
ACPI Enable
OSPM performs this transition by writing the ACPI_ENABLE value to the SMI_CMD, which generates an event to the hardware to transition the platform into ACPI mode. When hardware has finished the transition, it sets the SCI_EN bit and returns control back to OSPM.
ACPI Disable
While in the G0 “working state,” OSPM can request a transition to Legacy mode by writing the ACPI_DISABLE value to the SMI_CMD register, which results in the hardware going into legacy mode and resetting the SCI_EN bit LOW.
=======================================================================
ACPI Enable
由OS去寫ACPI_ENABLE的值到SMI_CMD port,會由BIOS所註冊的ACPI Enable的SMI handler去處理將SCI_EN bit設起來,在這handler裡,OEM可以自行加入程式碼以達到一些特殊的需求,再將控制權交還給BIOS。
ACPI Disable
在ACPI_ENABLE下,也可由OS去寫ACPI_DISABLE的值到SMI_CMD port,會由BIOS所註冊的ACPI Disable的SMI handler去處理將SCI_EN bit清為零。
OSPM performs this transition by writing the ACPI_ENABLE value to the SMI_CMD, which generates an event to the hardware to transition the platform into ACPI mode. When hardware has finished the transition, it sets the SCI_EN bit and returns control back to OSPM.
ACPI Disable
While in the G0 “working state,” OSPM can request a transition to Legacy mode by writing the ACPI_DISABLE value to the SMI_CMD register, which results in the hardware going into legacy mode and resetting the SCI_EN bit LOW.
=======================================================================
ACPI Enable
由OS去寫ACPI_ENABLE的值到SMI_CMD port,會由BIOS所註冊的ACPI Enable的SMI handler去處理將SCI_EN bit設起來,在這handler裡,OEM可以自行加入程式碼以達到一些特殊的需求,再將控制權交還給BIOS。
ACPI Disable
在ACPI_ENABLE下,也可由OS去寫ACPI_DISABLE的值到SMI_CMD port,會由BIOS所註冊的ACPI Disable的SMI handler去處理將SCI_EN bit清為零。
Can't Access PCIe Network IO Resource at early POST
Question:
Can't access PCIe network IO resource at early POST issue.
Solution:
The PCI command register set to 0x07 and assign IO resource forPCIe network device. It also needs to set the PCI command register set to 0x07 on PCIe bridge.
=======================================================================
問題:
最近有遇到一個要存取掛在PCIe Bridge底下的PCIe網卡設定問題,狀況是無法在early POST時存取到PCIe網卡底下的IO resource。
解決方案:
PCIe網卡的PCI command register設成0x07以及指派IO resource外,注意也需要把PCIe Bridge的PCI command register設成0x07。
Can't access PCIe network IO resource at early POST issue.
Solution:
The PCI command register set to 0x07 and assign IO resource forPCIe network device. It also needs to set the PCI command register set to 0x07 on PCIe bridge.
=======================================================================
問題:
最近有遇到一個要存取掛在PCIe Bridge底下的PCIe網卡設定問題,狀況是無法在early POST時存取到PCIe網卡底下的IO resource。
解決方案:
PCIe網卡的PCI command register設成0x07以及指派IO resource外,注意也需要把PCIe Bridge的PCI command register設成0x07。
Set Watch Dog Timer for AMD chipset
WatchDogTimerConfig - RW - 8 bits [PM_Reg:4Ch]
WatchDogDisable bit 0 - 0 / 1 Enable/Disable WatchDog function
WatchDogFreq bit 2:1 00 / 11 32KHz/1Hz
WatchDogTimerEn - RW - 32 bits [PM_Reg:48h]
WatchDogDecodeEn bit 0 - 1 to enable decoding of WatchDogTimer address
WatchDogBase bit 31:3 - WatchDogTimer base address
WatchDogControl - RW - 32 bits - [WD_Mem_Reg:00h]
WatchDogRunStopB bit 0 - 0/1 Watchdog is in the Stopped/Running state
WatchDogAction bit 2 - 0/1 System reset/power off
WatchDogDisable bit 3 - 0/1 Enable/Disable
WatchDogTrigger (WO) bit 7 - write one to trigger the watchdog
WatchDogCount - RW - 32 bits - [WD_Mem_Reg:04h]
WatchDogCount bit 15:0 - Set Count
1. Set the WatchDogDisable to enable and WatchDogFreq in WatchDogTimerConfig register.
2. Get the WatchDogBase address
3. Set the WatchDogCount
4. Set the WatchDogRunStopB to run
5. Trigger the WatchDogTrigger
=========================================================================
1. 設定WatchDogTimerConfig的WatchDogDisable位元及設定WatchDogFreq的頻率.
2. 讀取WatchDogBase的位址
3. 設定WatchDogCount去決定最大計數個數
4. 設定WatchDogRunStopB成執行模式
5. 設定WatchDogTrigger位元去啟動Watch Dog Timer
WatchDogDisable bit 0 - 0 / 1 Enable/Disable WatchDog function
WatchDogFreq bit 2:1 00 / 11 32KHz/1Hz
WatchDogTimerEn - RW - 32 bits [PM_Reg:48h]
WatchDogDecodeEn bit 0 - 1 to enable decoding of WatchDogTimer address
WatchDogBase bit 31:3 - WatchDogTimer base address
WatchDogControl - RW - 32 bits - [WD_Mem_Reg:00h]
WatchDogRunStopB bit 0 - 0/1 Watchdog is in the Stopped/Running state
WatchDogAction bit 2 - 0/1 System reset/power off
WatchDogDisable bit 3 - 0/1 Enable/Disable
WatchDogTrigger (WO) bit 7 - write one to trigger the watchdog
WatchDogCount - RW - 32 bits - [WD_Mem_Reg:04h]
WatchDogCount bit 15:0 - Set Count
1. Set the WatchDogDisable to enable and WatchDogFreq in WatchDogTimerConfig register.
2. Get the WatchDogBase address
3. Set the WatchDogCount
4. Set the WatchDogRunStopB to run
5. Trigger the WatchDogTrigger
=========================================================================
1. 設定WatchDogTimerConfig的WatchDogDisable位元及設定WatchDogFreq的頻率.
2. 讀取WatchDogBase的位址
3. 設定WatchDogCount去決定最大計數個數
4. 設定WatchDogRunStopB成執行模式
5. 設定WatchDogTrigger位元去啟動Watch Dog Timer
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