Set Watch Dog Timer for AMD chipset

WatchDogTimerConfig - RW - 8 bits [PM_Reg:4Ch]
WatchDogDisable         bit 0    -  0 / 1 Enable/Disable WatchDog function
WatchDogFreq             bit 2:1    00 / 11  32KHz/1Hz

WatchDogTimerEn - RW - 32 bits [PM_Reg:48h]
WatchDogDecodeEn    bit 0 - 1 to enable decoding of WatchDogTimer address
WatchDogBase             bit 31:3 - WatchDogTimer base address

WatchDogControl - RW - 32 bits - [WD_Mem_Reg:00h]
WatchDogRunStopB      bit 0 - 0/1 Watchdog is in the Stopped/Running state
WatchDogAction            bit 2 - 0/1 System reset/power off
WatchDogDisable           bit 3 - 0/1 Enable/Disable
WatchDogTrigger (WO) bit 7 - write one to trigger the watchdog

WatchDogCount - RW - 32 bits - [WD_Mem_Reg:04h]
WatchDogCount            bit 15:0 - Set Count

1. Set the WatchDogDisable to enable and WatchDogFreq in WatchDogTimerConfig register.
2. Get the WatchDogBase address
3. Set the WatchDogCount
4. Set the WatchDogRunStopB  to run
5. Trigger the WatchDogTrigger

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1. 設定WatchDogTimerConfig的WatchDogDisable位元及設定WatchDogFreq的頻率.
2. 讀取WatchDogBase的位址
3. 設定WatchDogCount去決定最大計數個數
4. 設定WatchDogRunStopB成執行模式
5. 設定WatchDogTrigger位元去啟動Watch Dog Timer